FPGA Implemenation of Multi-layer Perceptrons for Speech Recognition

In this paper, a method for designing and implementing of Multilayer Percepton (MLP) based on BP algorithm has been suggested. The method has described a MLP on Register Transfer Level (RTL) using VHDL description language and implemented on Field Programmable Gate Array (FPGA) for speech recognition. Firstly, a multiplyaccumulate (MAC) unit, and sigmoid nonlinear function are implemented as a basic building units of the MLP. The MLP is trained by BP learning algorithm. The optimized parameters are obtained by Matlab simulation for off chip training design. The implementations have been developed and tested on Xilinx Spartan-IIIE XC3S500E FPGA chip for embedded systems using Xilinx ISE 10.1 software. The research also presents a summary of the performance cost and data throughput with regards to the speed and required computational resources. The proposed hardware architecture are found to be 6 times faster than the software implementation.